10G High speed backplane in 28 layers
<<BackSource: Time:2014/8/27 0:00:00
| 【TYPE】： | 10G High speed backplane in 28 layers |
| 【Difficulty】： | Thousands of 10G high-speed differential pairs in this backplane. Signal integrity is very important for this design. |
| 【Solution】： | With the experienced in PCB design and manufacture for many years. EDADOC co-work with the PCB suppliers and connector suppliers, and communication with customers closely. SI team is involved into this project. The SI process is Pre-simulation, Constraint driven PCB design, and Post simulation for verification. |
| 【Result】： | The first version of this project was debugged successfully. The quality of signal is fulfill with the Spec. |
